OpenVizsla

As we’ve mentioned before, the sheer quantity of pledges has opened the doors to many suppliers, we’ve had offers of help from all around the world, people are looking forward to getting the OpenVizsla hardware in their hands so that they can innovate around the platform, we think a great community will form around this device.

The development prototype has a number of additional features that will help the developers with the firmware and general usefulness of the device. We’ve added USB target port power monitoring (so that we’ll be able to graph power consumption during analysis), an additional CPLD that allows JTAG and serial debug signals to be rerouted to any of the other debuggable items on the board (either of the XMOS cores, the FPGA etc) and of course the on board FTDI JTAG and USB UART device.

Most of these debug features are only for the prototypes that will be sent to developers, but the majority of the footprints will be still available in the final device that ships, so you guys can add the functionality back onto the board if you require it, any code/tools that is used for debugging will be open-sourced, so should you wish to go in that direction you’ll hit the ground running!

Below is a screen-shot of the last development board layout, this shows a sneak-peek of the design (note, this was before the additional hardware mentioned above was added and those changes have not been routed yet, so this doesn’t show those) and of course this isn’t the design of the finaldevice, the PonyPort will likely change and also some of the other components and the shape may be altered.

We’ve had several emails asking if upgrades from lower pledges to the $150+ ‘bare-bones board’ or the $250+ tier is possible, and the answer to this is yes! If you would like to receive one of the first boards when the first production run happens, then please change your pledge soon (so that we can get the numbers and planning correct now).

Thanks guys, you all rock!

previously seen on the kickstarter page